28 Feb 2018
State-of-the-art lithography tools are poised for a manufacturing ramp next year, but questions remain over the full extent of the technology’s future deployment.
Plenary and keynote speakers at SPIE’s Advanced Lithography conference have described extreme ultraviolet (EUV) lithography as being “on the brink” of full-volume production for the next generation of semiconductor chips – but indicated that the full extent of the technology’s impact over the coming decade remains uncertain.
A series of presentations by senior executives and managers from key tool maker ASML, chip maker GlobalFoundries and others confirmed that, after around three decades of development – costing billions of dollars – EUV tools are now showing the kind of productivity and performance needed for initial adoption in high-volume manufacturing (HVM).
After a look back on 30 years of key developments, from the first EUV-produced transistor in 1996 to ASML’s latest “NXE:3400B” tools, GlobalFoundries’ VP of technology research George Gomba told delegates that EUV lithography was “positioned for the 7 nm [chip manufacturing] node”, and that it would lead to true innovations for future nodes and next-generation processor designs - provided that challenges associated with tool productivity, photomasks, and random effects referred to as “stochastics” can all be overcome.
“It’s been thirty years in the making and has been a lot of hard work,” Gomba said in his keynote talk at the San Jose event. “And there’s a lot more hard work to come.”
In another keynote talk Roderik van Es, ASML’s director of product management for EUV, said he was “very confident” that the company was making the right moves to ensure the technology is ready for HVM insertion in 2019 – seen as the key year in which EUV systems will be cranked up at TSMC, Samsung and elsewhere.
And in just the past few days, added van Es, EUV tools fitted with the latest laser-powered sources at ASML’s own factory have demonstrated best-ever productivity levels of 140 wafers per hour.
ASML’s productivity roadmap
That latest improvement, up from 104 wafers per hour a year ago and 126 wafers per hour in late 2017, is thanks to a new design of the high-power CO2 laser system that generates EUV radiation in the lithography tool’s source chamber when it blasts a series of tin droplets.
“We have completed a major redesign of the CO2 laser system to support 250 W [EUV] source power,” reported van Es. He added that the final, industrialized version of that source was completed in late 2017, following a year of development work on an initial prototype that included reducing its volume by a factor of 20 to fit the commercial EUV tool’s layout and enable in-the-field upgrades.
“We are very pleased with the source,” he added, showing data indicating that the 250 W power level was maintained for 75 hours with stable performance – good enough to make half a million wafer exposures, with 99.995 per cent at the required EUV “dose” specification.
Van Es and the ASML development team are now looking towards increasing the source power to 300 W, partly to ensure that the 125 wafers per hour productivity level can be hit both with and without a pellicle, a component that protects wafers from tiny particles that can create defects but which absorbs some of the EUV power.
Highlighting how the throughput metric has risen from just 0.05 wafers per hour with initial prototype EUV kit used at imec back in 2006, to 9 wafers per hour with ASML’s “NXE:3350B” tool in early 2014, and now to the latest 140 wafers per hour level just demonstrated, van Es concluded:
“We’ve made steady progress, are very pleased to be going in the right direction, and happy to bring this to customers as soon as possible.”
He added that with partners showing “great” EUV lithography performance results for overlay, focus uniformity, and other key metrics at high source power, significant progress has been made in all key areas towards insertion in HVM.
Samsung’s $6BN EUV line
That confidence will have been backed up by last week’s announcement from Samsung – one of ASML’s key customers – that it had broken ground on a new EUV line at its under-construction facility in Hwaseong, Korea.
“The new facility is expected to be completed within the second half of 2019 and start production ramp-up in 2020,” Samsung stated. “The initial investment in this new EUV line is projected to reach $6 billion by 2020 and additional investment will be determined depending on market circumstances.”
Samsung has decided to use EUV to produce certain layers in its 7 nm node “LPP” (Low Power Plus) chip process, with the cutting-edge technology expected to play a greater role when chip makers reach the subsequent 5 nm mode, which will require even smaller features.
But while the implementation of EUV - in tandem with more conventional deep-UV (DUV) lithography equipment based around 193 nm excimer lasers - looks pretty certain for the 7 nm and 5 nm nodes, question marks remain over its utilization for subsequent process designs, as hinted at by Samsung's "market circumstances" language.
In his SPIE Advanced Lithography plenary talk, the retired Intel fellow Yan Borodovsky noted that the question was no longer “if” or “when” EUV would be used, but “how well” it would be implemented.
For chip makers buying ASML tools selling for approximately the same price as a new Boeing 737, that ability to deploy the technology in an increasing number of manufacturing steps and processes is fundamental to reducing the future cost of making each “pixel” on a wafer – and ensuring that Moore’s law continues to apply.
While Borodovsky pointed out that the burden of “EUV transformation readiness” was now shifting from tool developers to logic and memory chip manufacturers, he also noted that there would inevitably be some hidden “gotchas” to contend with, alongside anticipated challenges with photoresists and pellicles.
High-NA optics for EUV tools
Fellow plenary speaker Stephen Hsu, from ASML’s "Brion" computational lithography unit, offered up several suggestions of how EUV technology might be refined for future nodes and process steps.
That comes in the form of “resolution enhancement techniques” (RETs), building on what has worked for DUV lithography, including immersion and multi-patterning approaches that have been deployed ahead of EUV’s arrival.
Options include wavefront engineering for better phase control and – in the longer term – the development of high-numerical aperture (high-NA) reflective optics with ASML’s key partner Zeiss.
A major challenge with high-NA EUV optics is that the current generation of mirrors can only handle a small range of incident angles – with a “central obscuration” design under development to get around that problem.
But Hsu appeared confident that optical innovation would ensure continued, growing uptake of EUV, telling delegates: “High-NA EUV with RETs will enable sub-5 nm node shrink using single-exposure patterning."
His colleague Roderik van Es showed an ASML product roadmap indicating that the high-NA generation of systems could be expected in late 2023 or 2024, by which time productivity is slated to have reached 185 wafers per hour. That should come after the company’s “NXE:3400C” tool appears, in around two years from now.
Whether productivity gains will be sufficient to support EUV’s emulation of DUV with multi-patterning techniques remains open to question, but Hsu and van Es both sounded optimistic notes on the nearer-term future of EUV.
“EUV has put us back on the scaling roadmap in terms of cost-per-pixel,” said van Es, with Hsu adding: “This year EUV is marching towards HVM [at] full speed. Let’s make this wavelength transition as soon, and as smooth, as possible.”