Salience Labs raises $11.5 million for photonics-based processor

17 May 2022

Ultra high-speed chips combining photonics and electronics will accelerate AI advances.

Salience Labs, spun-out of the University of Oxford and the University of Münster in 2021 to develop photonics-based multi-chip processors, has raised $11.5 million in seed funding.

The money will facilitate work on ultra high-speed multi-chip technology, based on packaging a photonics chip together with standard electronics. This architecture has been designed from first principles for volume manufacture, and for fabrication with production-level foundries using standard CMOS processes.

Salience Labs believes the processor should allow massively parallel, ultra-high throughput processing performance on a single chip, bringing power-efficient exascale computing to a wide array of new and existing AI processes and applications.

"The world needs ever faster chips to grow AI capability, but the semiconductor industry cannot keep pace with this demand," commented Vaysh Kewada, Salience Labs CEO.

"We’re solving this with our proprietary 'on-memory compute' architecture which combines the ultra-fast speed of photonics, the flexibility of electronics and the manufacturability of CMOS. This will usher in a new era of processing, where AI becomes ubiquitous."

The same principles could have an impact beyond AI, potentially allowing neural networks to grow larger and achieve more precise data analysis. Clinical data processing for diagnosis and evaluation of data from sensors in autonomous vehicles could also ultimately benefit from this approach.

According to Salience Labs data, its new chip architecture involves the photonic processing mapping directly on top of the Static Random Access Memory (SRAM). This novel on-memory compute principle is said to be inherently faster and can be adapted to the application-specific requirements of different market verticals, making it ideal for realizing AI use-cases in communications, robotics, vision systems, healthcare and other data workloads.

Pioneering yet pragmatic solution to the demands of AI

In a 2021 Nature paper a project led by Münster's Johannes Feldmann, now Salience Labs CTO, outlined a computationally specific integrated photonic hardware accelerator (tensor core) that is capable of operating at speeds of trillions of multiply-accumulate operations per second.

"The tensor core can be considered as the optical analogue of an application-specific integrated circuit," noted the group. "It achieves parallelized photonic in-memory computing using phase-change-material memory arrays and photonic chip-based optical frequency combs. The computation is reduced to measuring the optical transmission of reconfigurable and non-resonant passive components and can operate at a bandwidth exceeding 14 gigahertz, limited only by the speed of the modulators and photodetectors."

This approach is designed to exploit a group of current breakthroughs in chip-related research, including the integration of soliton microcombs at microwave line rates, ultra-low-loss silicon nitride waveguides, and high-speed on-chip detectors and modulators.

"Given recent advances, our approach provides a path towards full complementary metal-oxide-semiconductor (CMOS) wafer-scale integration of the photonic tensor core," noted the group in its Nature paper.

Alexis Zervoglos of partner Oxford Science Enterprises commented that the Salience Labs technology was "a pioneering yet pragmatic solution to the widening gap between AI processing demand and semiconductor industry supply. By leveraging photonics in a novel way, Salience Labs is set to make unprecedented advances, transforming existing AI applications and opening up new addressable horizons."