05 May 2022
The patterning ecosystem around imec and ASML's lithography system is taking shape.SPIE Advanced Lithography + Patterning Conference, Belgian electronics research center imec presented the latest results from its Joint High-NA Lab and the patterning ecosystem around extreme ultraviolet (EUV) lithography systems being developed there in partnership with ASML.
The lab, established in 2018, will be centered around the first 0.55NA EUV lithography prototype tool, a high-NA EUV system known as the EXE:5000.
Imec anticipates the first generation of commercial EUV lithography tools arriving in 2023, with 2025 seeing "the introduction of the first high-NA EUV lithography equipment in high-volume manufacturing environments."
For that timeline to be realized, a significant amount of research currently underway needs to be completed, with the latest data presented in a dozen individual contributions to the SPIE conference.
"It is our role, in tight collaboration with the global patterning ecosystem, to ensure timely availability of advanced resist materials, photomasks, metrology techniques, anamorphic imaging strategies and patterning techniques, to fully benefit from the resolution gain offered by the High-NA EUV lithography scanner," commented imec CEO Luc Van den hove. "At this year's conference we have 12 contributions in the realm of High-NA EUV lithography, showing that we are well on track to prepare for ecosystem readiness."
The presentations covered three broad topics, one being processes and material optimization in anticipation of the High-NA EUV prototyping system. Imec described how line-edge roughness (LER) and pattern collapse are the most critical parameters for patterning lines/spaces with thin resist films, and strategies for mitigating pattern roughness by tuning illumination and mask conditions have been developed.
Mask design rules getting tighter
Another research effort is directed at tailoring the metrology needed, since a transition to smaller feature sizes and thinner resist films presents significant challenges, not least the need for imaging of individual features below 10 nanometers in size.
"Image contrast can be significantly improved by tweaking the operation conditions of existing metrology tools," commented imec's Kurt Ronse. "Image analysis and defect classification are further enhanced by dedicated software, supported by deep learning frameworks. In close collaboration with its metrology suppliers, imec explores alternative metrology techniques for reliably measuring small features, such as high-throughput scanning probe metrology and low-voltage aberration corrected SEM."
The third topic involves addressing high-NA EUV mask-specific challenges, specifically mask multilayer ripple and absorber line-edge roughness, since imec has determined that mask imperfections are increasingly impacting the final wafer pattern.
"Mask design rules need to become tighter, and these findings allow us to identify mask specifications for high-NA EUV lithography," said Ronse. "Together with ASML and our material suppliers, we explore novel materials and architectures for the mask absorber, which carries the pattern. We have for the first time performed exposures to evaluate the impact of using low-n attenuated phase shift masks, and masks with low-n absorber materials are shown to improve the mask 3D effects on the wafer, and help to increase the high-NA depth of focus."