22 Oct 2018
Accelerated development should see next-generation tool shipped by the end of 2022.
Engineers at the Belgian electronics research center imec and lithography equipment giant ASML are establishing a new laboratory to accelerate the development of next-generation extreme ultraviolet (EUV) optics for patterning semiconductor chips.
Part of a wider collaboration between the two that has already run for three decades, the high-numerical aperture (high-NA) EUV laboratory will aim to shrink device features beyond even what is possible with the current, initial generation of EUV equipment.
Beyond 3 nm
Current EUV tools, which offer an NA of 0.33, are now entering a production ramp at a handful of chip companies, with the first commercial devices manufactured using the technology expected to appear imminently.
While that initial generation of EUV systems should be sufficient for the next few years, it is thought that the high-NA optics will be needed to scale beyond the so-called “3 nm node”. The plan is to raise the NA to 0.55, and if all goes according to plan the future generation of EUV lithography equipment should be ready to begin shipping for test runs by the end of 2022, with full-scale production a few years after.
imec announced in a release: “In this lab, researchers from both organizations will experiment with the next generation of EUV lithography at higher NA. Systems with a higher NA project the EUV light onto the wafer under larger angles, improving resolution, and enabling printing of smaller features.”
A new high-NA EUV system, which will be known as the “EXE:5000”, will be installed in the joint research laboratory, although initial projects are already said to be under way.
Just last week ASML’s executive team told an investor conference call that the company’s research and development spending would increase significantly as both the high-NA development and next year’s release of the “NXE:3400C”, based on the current design but with higher source power, were brought forward.
CEO Peter Wennink said in that call: “I think what you will see going forward is that high-NA will be introduced in high-volume manufacturing towards the middle of next decade. Then you will see a very clear mix of our ‘low-NA’ layers and the use of ‘high-NA layers. They're going to be used next to each other.”
Wennink explained that the future technology would not be expected to cannibalize much of the current “low-NA” EUV capability, rather it would address the additional critical patterning layers.
The company’s elevated spending on related research is expected to peak over the next two or three years, with the very first high-NA tools shipping in 2022.
imec’s CEO Luc Van den hove said of the plans: “The new EUV scanners and ASML metrology equipment will allow our industry partners to perform collaborative research on the most advanced and industry relevant lithography and metrology equipment.”
Optics firm Carl Zeiss is another of the key players involved in EUV development, with ASML having invested a billion euros in the German firm’s semiconductor technology division as part of a plan designed to ensure a successful outcome.
The already complex reflective optics needed for EUV become even more complicated when it comes to high-NA projection of light. Different shapes could be used to achieve the 0.55 NA, for example “extreme” aspheres or anamorphic designs analogous to those used in the visible spectrum for cinematography - but that complexity means that current EUV tools cannot be retro-fitted with the high-NA design.
ASML’s CTO Martin van den Brink said in the imec release: “Access to the most advanced semiconductor lithography tools is vital for exploration and determining the paths to future generations of semiconductor devices and applications.
“imec’s researchers and customers can be sure of the most up to date holistic lithography technology for many years to come. The semiconductor industry and consumers and businesses around the world will benefit from the fruits of imec’s work over the next decade, resulting in continuing improvements in microchip cost and performance.”