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CMOS technology moves to the next generation

11 Nov 2008

Developments in complementary metal oxide semiconductor (CMOS) technology allow the sensors to penetrate into high-performance applications that were previously not practical. Lars Hansen of Basler Vision Technologies, Germany, describes the current state of the art.

In the past, charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) sensors performed in different arenas. CCD sensors were used in applications where exceptional image quality was required but lower speeds were acceptable. CMOS sensors were known for their fast speeds, but less for image quality. The newest CMOS sensors now combine both high speed and excellent image quality, and are rapidly becoming more popular in both area-scan and line-scan machine-vision applications.

CCD and CMOS sensor technology
The history of digital imaging started in 1970 with the development of CCDs. Initially envisioned as data-storage devices, it was quickly recognized that these components were light sensitive and that they produced a signal proportional to the amount of light applied. The basic principle behind interlaced CCDs is a set of transfer registers beside the light-sensitive surface of the pixels in the CCD. The transfer registers sequentially transport charges from the pixels to shift registers below the sensor (figure 1). CCD pixels can have a fill factor of up to 100%, which means that nearly the entire pixel is light sensitive. The drawback of the charge "transport system" used in CCDs is a limitation on the frame or the line rate (this will be discussed more later on). CCDs provide a relatively low noise level, which leads to very good image quality. The technology advanced quickly and CCDs were used more and more in digital still cameras, astronomy, machine vision, video cameras, fax machines and in many other applications.

CMOS sensors are characterized by having parts of the electronics, the read-out system and the illumination control located directly adjacent to the photosensitive surface. One main advantage of this design is that each pixel can be controlled and read out directly. A drawback is that a part of each pixel is occupied by electronic components, which reduces the fill factor (see figures 2 and 3). CMOS technology allows a variety of both analogue and digital functions to be integrated directly into the sensor. This means that analogue data can be amplified and converted into a digital signal right on the chip. Memory, timing generators and other preprocessing steps can also be integrated.

Where speed is vital
Over the last decade, the pressure to increase the throughput of industrial production systems has grown continuously. This requires faster acquisition speeds in digital-vision products, and there is an ongoing demand to increase the efficiency even further. A precondition for meeting this demand in digital cameras is the ability to deliver growing data rates for both area-scan and line-scan cameras. Line-scan cameras in particular are used in systems that perform endless inspection (e.g. surface inspection of paper, lamin-ates or printed goods) where the speed is an essential factor.

Sensor technology improvements
Until recently, most line-scan cameras have been equipped with CCD imaging sensors. In slower applications, CCD sensors produce excellent image quality, but when operating at higher speeds they face physical limitations. In high-speed applications, the driving circuits for a CCD sensor must work at high frequency against the high capacitive load of the CCD shift registers. This results in the heating of the sensor and the camera electronics, and consumes a great deal of power. To handle high speed, CCD sensors also need a multiplicity of output taps, with off-chip output amplifiers and analogue-to-digital converters (ADCs) on each tap. This makes CCD camera designs expensive and large in size.

A new conceptual approach for line-scan image sensors had to be found to overcome these limitations. Until the 1990s, CMOS technology suffered from low lithography resolution and the absence of fabrication processes optimized for imaging sensors. With the advent of CMOS active pixel sensor (CMOS-APS) technology, the sensors were virtually reinvented. CMOS-APS sensors rapidly became the first choice for high-speed area-scan imaging applications, in particular those with the column parallel ADC architecture introduced a decade ago.

Modern CMOS sensors not only exhibit superior performance in speed, but are more price-attractive than CCD sensors due to lower production costs. The latest CMOS sensor generation also exhibits excellent image quality, which used to be an exclusive strength of the CCD sector. Due to improvements in chip fabrication technology, recently developed CMOS sensors have excellent noise and homogeneity characteristics. The positive attributes of CCD technology have been transferred step by step into the specialized CMOS imaging sensor (CIS) fabrication processes. The result is that today's CMOS sensors combine the advantages of both technologies: the broad variety of CMOS circuit features and the superior imaging quality of CCD technology.

CMOS technology offers the possibility of combining the sensor's photodiodes with other on-chip CMOS circuits, which is not possible with CCD sensors. This is a major advantage compared to CCDs, where almost all electronics must be off-chip and added at a board level. The on-chip circuit capability makes amplifiers, correlated double sampling (CDS) circuits, mixed-signal circuits such as multiplexers, or digital circuits such as timing generators available to CMOS image sensor chip designers. The mobile phone industry demonstrated that the integration of additional intelligence into the imaging sensor can lead to dramatic decreases in price and to the miniaturization of components.

Advanced line-scan CMOS sensors
Comparing area-scan CMOS imaging sensors to line-scan CMOS imaging sensors reveals some important differences. In area-scan sensors, because the pixel electronics must fit next to each photodiode in the pixel grid, the area for electronics is limited. In line-scan sensors, the pixel electronics can be placed outside and the photodiode can fill the entire nominal pixel area. The consequences are:
• The line-scan CMOS sensor fill factor is actually 100%, whereas the fill factor for area-scan CMOS sensors is normally between 10 and 70% depending on factors such as sensor generation or pixel architecture.
• There is no pixel level transistor limit for line-scan CMOS sensors due to space requirements, whereas the number of transistors on CMOS area-scan sensors is usually limited to between one and a half and seven transistors per pixel depending on factors such as shutter technology or sensor architecture.

This second consequence in particular presents a wide solution space for line-scan CMOS pixel electronics. It allows much more advanced approaches to sensor architecture and read-out circuitry than those possible with standard area-scan CMOS sensors.

As an example, consider analogue gain. The photons collected by a pixel are converted to photoelectrons that are then converted into an analogue voltage (U), usually expressed in microvolts. This happens via a conversion capacity (C). To realize a high gain, i.e. a high U, C must be small. In area-scan sensors, C is defined by the photodiode junction capacity (CPD). CPD needs a certain minimum size (i.e. must have a certain minimum capacitance) to be able to collect photons over the entire pixel. In line-scan sensors, the integration can be performed by a second integration capacitor (Cint), the value of which is completely decoupled from the pixel properties. This yields a high analogue gain, which is an important prerequisite for good sensitivity.

Low sensor noise
The next important point is noise. A big part of the sensor read noise is the so-called 1/f noise. The largest portion of this 1/f noise can be eliminated by correlated double sampling (CDS). In common CMOS area-scan sensors, CDS is not performed because the required circuitry exceeds the amount of electronics that can typically be placed inside of a pixel. These area restrictions do not exist for CMOS line-scan sensors because the components are typically placed beside the pixel. That allows a true CDS circuit for each single pixel. Thus the excellent temporal noise values usually associated with CCDs can be achieved by a CMOS line-scan sensor that uses this architecture, and the CMOS sensor can compete with a CCD sensor in these terms.

With this new CMOS technology, it is possible to realize a dual line-scan CMOS sensor by placing two lines side by side (figure 4). This architecture presents even more possibilities and flexibility in use.

Because the read-out circuits are placed above and below the active pixel lines, each pixel has a 100% fill factor. And because there is no space between the two sensor lines, no spatial effects will occur. In addition, the line capture rate can be doubled by using the two lines, which means that a 70 kHz line rate in single-line mode will result in a 140 kHz rate in dual-line mode.

The advantages of the latest CMOS sensor designs were incorporated into the sprint series of line-scan cameras from Basler Vision Technologies. These cameras are available in 2, 4, and 8 k resolutions, and thanks to advanced CMOS technology, their line rate does not need to be reduced with the increased resolutions. This is unique and is not possible with CCD sensors.

The dual-line sensor employed in Basler sprint cameras can be used to scan each object line twice via time-delayed integration. This means that an object line is first scanned by sensor line A and the data is stored in the memory. The same object line is scanned a second time by sensor line B and this data is added to the previously stored data from A. This results not only in a doubling of the signal, but also reduces the noise by a factor of the square root of two, which in turn yields a signal-to-noise ratio improvement of 3 dB.

With CMOS line-scan technology the user can also set an area of interest. This means that only the pixels in the sensor actually required by the application will be read out. The result is a reduced amount of transmitted data and a speed increase that is linear to the resolution reduction. Such performance is not possible with CCD line-scan sensors.

To generate colour images, the dual-line sensor is equipped with a Bayer pattern filter. The first line in the sensor will collect red and green information, and the second line will collect green and blue information (figure 5).

With the improvements made in CMOS technology over the last few years, the shortening innovation cycles for CMOS development and the current trends in the marketplace, a shift from CCD to CMOS is expected in the line-scan arena to match the shift that has already happened in the area-scan sector.

We also expect that CMOS technology will play a major role in the machine-vision market and will continue to gain market share. This will be even more apparent in high-performance applications where the demand for higher line or frame rates and ultralow noise is increasing rapidly.

• Lars Hansen is a product manager at Basler Vision Technologies, Germany. For more information, visit Optics & Laser Europe magazine.

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