TSMC debuts silicon technologies at its North America Technology Symposium

02 May 2024

Chip foundry plans to qualify systems for small form factor pluggables in 2025.

The Santa Clara event kicked off TSMC symposia around the world.

Leading semiconductor foundry TSMC has this week unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies “for powering the next generation of AI innovations with silicon” at the company’s 2024 North America Technology Symposium.

The company debuted its TSMC A16 technology, featuring nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. It also introduced its System-on-Wafer (TSMC-SoW) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

This year marks the thirtieth anniversary of TSMC’s North America Technology Symposium, and more than 2,000 people attended, up from less than 100 30 years ago. The event in Santa Clara, California, kicks off TSMC symposia around the world through the year. The meet-up features an “Innovation Zone,” designed to highlight the technology achievements of TSMC’s emerging start-up customers.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “We are offering customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

TSMC’s latest processes, advanced packaging, and 3D chip technologies.

New technologies showcased

TSMC A16 Technology: With TSMC’s N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap. A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 suitaed to HPC products with complex signal routes and dense power delivery networks.
TSMC NanoFlex Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s development in design-technology co-optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance.
N4C Technology: Bringing TSMC’s technology to a broader range of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025. N4C offers area-efficient foundation IP and design rules that are fully compatible with the N4P, with better yield from die size reduction.
CoWoS, SoIC, and System-on-Wafer (TSMC-SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been an enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory stacks side by side on one interposer. At the same time, TSMC’s System on Integrated Chips (SoIC) has established itself as a solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.
Silicon Photonics Integration: TSMC is developing its Compact Universal Photonic Engine (COUPE™ ) technology to support growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.
Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.