CEA demonstrates ‘dynamically-routed’ optical router for photonic interposers

25 Feb 2026

ISSCC 2026 presentation shows 28 nm CMOS router achieving 18 ns frame-level path setup.

Researchers from CEA-List and CEA-Leti last week unveiled at ISSCC 2026 (the IEEE International Solid-State Circuits Conference) what they describe as “the first electro-optical router with dynamic, frame-level optical routing integrated with CMOS control logic.” This development could enable practical optical networking inside advanced chiplet-based packages.

The developers detailed their achievement in a conference paper “A 3.19pJ/bit Electro-Optical Router with 18ns Setup Frame-Level Routing and 1-6 Wavelength Flexible Link Capacity for Photonic Interposers”. This presents an electro-optical router implemented in 28 nm CMOS on a photonic interposer, capable of establishing optical paths in 18 ns. It can dynamically select up to six wavelengths per link, and achieves an energy efficiency of 3.19 pJ/bit with an active area of just 0.007 mm² per link.

CEA Leti stated, “Today’s optical interconnects are largely limited to static, point-to-point links, with initialization and training times ranging from microseconds to milliseconds. While suitable for board-level or rack-scale communication, those latencies prevent optical links from being used as a true networking fabric inside multi-die packages.”

The router addresses this gap by integrating optical switching, routing control, serializer/deserializer, and clocking logic directly with silicon photonics. The result is a dynamically-routed optical interconnect that operates at nanosecond timescales, enabling optical communication across centimeter-scale interposers with responsiveness previously limited to short electrical links.

It supports frame-level routing, allowing optical paths to be established and torn down on demand, and adjusts link capacity dynamically by selecting between one and six wavelengths, according to application needs. This flexibility enables efficient use of optical bandwidth, while maintaining ultra-low latency. The prototype is fabricated in a 28 nm CMOS process and integrated on a photonic interposer. Compact analog drivers, combined with standard-cell-based SerDes and clocking circuits, enable dense integration of optical endpoints close to compute and memory resources.

Integrated dynamic routing

This is said to be the first demonstration of dynamic optical routing in an integrated photonic switch that includes CMOS logic up to the protocol level. Previous optical switch demonstrations have typically relied on standalone photonic devices with static or slowly reconfigured paths that do not integrate the full driving, control, and routing logic required for packet-level operation.

In contrast, the new router operates as a miniature network switch inside the package, combining microring-based photonic devices with digital control logic to move data efficiently across the interposer. The new approach avoids power and latency penalties that scale with distance, relaxing constraints on data locality and enabling more flexible hardware architectures and software data placement.

“As chiplet systems continue to grow in scale and complexity, the ability to move data efficiently across the entire package becomes essential,” said CEA-List’s Yvain Thonnart, lead author of the paper. “Our goal was to demonstrate that photonic links can provide that reach without sacrificing the flexibility designers expect from modern interconnects. This router is a step toward practical, dynamically routed optical networks that fit within standard CMOS design flows and real product constraints.”