Helios project shows silicon laser progress

19 Nov 2010

EU-funded project to make silicon photonics technology widely available demonstrates CMOS-compatible laser and modulator fabrication processes.

Project partners working on the “Helios” European project to develop silicon photonics have demonstrated a laser and a 10 Gb/s modulator in a CMOS-compatible manufacturing process.

The 19-strong consortium, which is co-ordinated by CEA-Leti in France, is now two years into the project. Its primary aim is to develop a high-volume process for producing devices that can be transferred to any interested silicon device manufacturer.

Similar to Intel, the Helios team’s “silicon” lasers are based on a hybrid form that incorporates indium phosphide as the light emitting material. The Fabry-Pérot laser is fabricated by first bonding InP material to the top of a silicon wafer, and then using standard CMOS processing equipment for the remainder of the device production steps.

In the Helios approach, an InP wafer already incorporating a semiconductor heterostructure for light production is first diced up, with the individual die then bonded to a much larger silicon wafer. The InP substrate material is then removed from each of the laser die.

Laser performance
CEA-Leti’s Laurent Fulbert, who manages the Helios project, told optics.org that the main difference between the Helios method and that developed by an Intel/UCSB collaboration is that in the Helios approach the bonding thickness tolerance is more relaxed, which makes device fabrication somewhat easier.

In terms of device characteristics, the Helios laser has shown a threshold current of 50 mA and an output power of up to 3 mW. Those results are close to the project’s objectives (<35 mA and 2 mW), although there is more room for improvement regarding operating temperature, which needs to be increased from about 20 °C currently to 65 °C.

The consortium’s existing silicon modulator shows an extinction ratio of 7 dB at 10 Gb/s, while the first characterization results from a 40 Gb/s version are expected next year – the third of the four-year Helios effort. Other silicon photonics building-blocks that have already been developed under Helios include highly responsive photodiodes (0.8-1 A/W), and efficient passive waveguides for modulation and demodulation functions, meaning that many of the components required to significantly reduce the cost of photonic systems are either in place or well on the way to being developed.

“The capability of manufacturing optical components within the CMOS-processing infrastructure is key to realizing the potential of silicon photonics,” said Fulbert. “The Helios partners are focused on bringing this technology to foundries and component manufacturers for high-volume applications.”

At the moment, the InP manufacturing steps are performed at either the Alcatel-Thales III-V Laboratory in France, or at IMEC in Belgium, while the CMOS steps are performed at either IMEC or CEA-Leti.

By the end of the four-year project, Fulbert says that the consortium is aiming to have demonstrated a 16 x 10 Gb/s transmitter based entirely on components manufactured using CMOS processing. Products based on the technology should end up enabling a range of low-cost photonic applications such as chip-to-chip and rack-to-rack optical interconnects to replace copper links in data centers and servers.