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Topologies for an addressable VCSEL array chip include (a) a column addressable chip with stripes of emitters, multiple anode bond-pads and a backside cathode (c) a matrix addressable chip with anode bond-pads for each column and cathode bond-pads for each row. Corresponding schematics are shown respectively in (b) and (d).
Topologies for an addressable VCSEL array chip include (a) a column addressable chip with stripes of emitters, multiple anode bond-pads and a backside cathode (c) a matrix addressable chip with anode bond-pads for each column and cathode bond-pads for each row. Corresponding schematics are shown respectively in (b) and (d). Images: Lumentum.
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