20 Aug 2004
Researchers at IBM say they have developed a method that enables the fast, efficient manufacture of photodetectors that are compatible with CMOS production. Michael Hatcher reports.
Optical interconnects have long been heralded as a possible way of solving communication bottlenecks at the chip level, but one of the key problems holding back the technology has been finding a method of making optical devices that is compatible with conventional chip manufacture.
Now, researchers at IBM appear to have developed a technique that could solve the problem at the detector end of the link. Led by Steve Koester, the team is based at the IBM T J Watson Research Center in Yorktown Heights, NY. It has made germanium-based PIN photodetectors using a method that it claims is compatible with CMOS technology.
Koester and colleagues made the breakthrough by depositing germanium films on ultrathin silicon-on-insulator (SOI) substrates. Germanium-based detectors have been developed previously for optical telecommunications, but only at wavelengths of 1.3 and 1.55 µm, which are principally used in relatively long-range links.
"It is a little-appreciated fact that germanium is an extremely efficient absorber at 850 nm, about 50 times better than silicon and with an absorption depth of only a few hundred nanometers," Koester told Compound Semiconductor. This is also the emission wavelength of GaAs-VCSEL sources, generally used in short-range datacom applications.
"We had the idea of making an extremely fast photodetector using germanium," Koester continued. "The catch is that silicon is also a weak absorber at this wavelength. So we adapted the germanium-on-insulator [GeOI] devices that had been made previously."
According to IBM, using current silicon photodetectors in optical interconnects makes about as much sense as trying to use transistor technology from the 1960s in today's microprocessors - i.e. no sense at all.
Silicon detectors have been pushed to reasonable speeds (approaching 10 GHz) using concepts such as IBM's lateral trench detectors, where deep trenches of alternating p and n contacts are fabricated in the devices, and the electric field is perpendicular to the direction of the light hitting the detector. However, the high capacitance of the deep trenches ultimately limits the speed at which these detectors can operate. One of the key advantages of the GeOI detectors, says Koester, is their inherent scalability.
Resonant-cavity structures offer high efficiency coupled with a speed similar to that of the GeOI detectors. As Koester points out, however, these structures are very difficult to fabricate: "[These devices] feature alternating Bragg reflecting mirrors that are hard to integrate, and they only collect a lot of light at the resonant frequency." And although InGaAs is a very good detector in the near-infrared, the III-V material will always be difficult to integrate with silicon-chip architecture.
The IBM team takes a silicon substrate and fabricates an SOI layer on it beneath a layer of germanium (figure 1). The substrate is isolated, allowing the efficient collection of charge carriers generated in the germanium layer. Germanium has a high absorption coefficient, so this detector layer can be made ultrathin and, consequently, the device can operate at a high speed. "We've combined the idea of germanium-on-silicon with putting it on an insulator," Koester said.
The structure then undergoes cyclic annealing at 780-900 ºC to reduce defect densities. In this step the buried oxide limits silicon diffusion into the germanium layer - a process that can reduce detector efficiency by increasing the bandgap if it is left unchecked.
According to Koester, a key aspect of the device's fabrication is maintaining a good interface between the germanium and silicon layers. Owing to the lattice mismatch, germanium tends to ball up and tries to grow three-dimensionally, while it is also sensitive to interface contamination.
With a bandwidth of 29 GHz, the GeOI detectors already exhibit a speed that is fast enough to support optical links operating at more than 50 Gbps. The devices have n- and p-type implanted contacts and interdigitated titanium/aluminum electrodes. The oxide-isolated mesas are patterned using optical lithography, while all other levels are patterned using an electron-beam tool. An electrode spacing of either 0.4 or 0.6 µm is generally used.
For the semiconductor industry to even consider incorporating such devices in chip architecture, it is crucial for the technology to be readily scalable to higher performance levels. Koester says that this is possible with the GeOI detectors. "You can always make a photodetector faster by making the absorbing layer thinner, until you're limited by basic transport phenomena," he said. "But then it may be inefficient and absorb hardly any light. The trick is to combine speed and efficiency."
* IBM's progress with GeOI photodetectors comes less than a year after IBM and Agilent embarked on a separate three-year project that is focusing on the development of optical interconnects for board chip-level communication (see Compound Semiconductor October 2003 p16). *
Michael Hatcher is editor of Compound Semiconductor magazine.
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