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SPIE Advanced Lithography to advance the quest for ‘faster, smaller, cheaper’ chips

Date Announced: 22 Jan 2014

Hot topics include EUV, optical, next-generation lithography.

BELLINGHAM, Washington, USA, and CARDIFF, UK -- Hybrid and other "alternative" technologies for the faster, smaller, and cheaper chips increasingly required by the semiconductor industry will feature among hot topics at SPIE Advanced Lithography, 23-27 February in San Jose, California.

The annual symposium, presented by SPIE, the international society for optics and photonics, will include more than 650 technical papers in seven conferences devoted to applications, tools, patterning materials, and topics related to EUV lithography, metrology for microlithography, and alternative lithographic techniques.

Technical sessions will be complemented by panel discussions, professional development courses, and a two-day exhibition (25-26 February) featuring more than 50 companies.

"Lithography continues to be an exciting field, and the SPIE Advanced Lithography Symposium continues to be a great place to come and learn about the newest developments," said symposium chair Harry Levinson of GLOBALFOUNDRIES.

Expertise will be on hand to address the challenge.

"To start the week, we are fortunate to have three distinguished plenary-session speakers who will share their visions of technology with us. The technical sessions look to be interesting across all seven conferences. ," Levinson noted. "Papers, including invited ones, are authored by a broad range of people from across academia, chip companies, equipment and materials suppliers, and research consortia."

The conference EUV lithography has the most presentations this year, while the growing number of papers reporting advances in optical (non-EUV) and next-generation lithography (NGL), metrology, and inspection illustrate the interest in directed self-assembly (DSA), smart resists, and combinations of novel lithographic techniques in chip manufacturing of the future. There are many outstanding submissions in "mature" optical lithography, DFM, and metrology, and several strong joint sessions reflect the integrated nature of lithography, Levinson said.

Of particular note, said symposium co-chair Mircea Dusa of ASML US, are panel discussions on "Extending the end of CMOS through nanotechnology" and "Alternative forms of scaling," and conference sessions on multipatterning with design optimization and exposure tools extendibility.

The all-conference plenary session will open with a talk from 2013 SPIE President William Arnold, chief scientist and vice president of ASML's Technology Development Center. Other plenary speakers are:

• Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics, will discuss advances in electronic design automation (EDA) and working with patterns throughout the design and manufacturing flow.

• Akihisa Sekiguchi, corporate vice president and deputy general manager at Tokyo Electron Ltd. (TEL), will give a talk on the future and alternative forms of scaling.

New topics among the 13 professional development courses are on computational lithography and management of metrology toolset.

Accepted papers will be published in the SPIE Digital Library as soon as approved after the meeting, and in print volumes and digital collections.

Source: SPIE

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