14 Mar 2017
Industry association SEMI says equipment bookings jumped 24% on 2015 figure, as chip makers report EUV lithography progress.
Spending on equipment used in semiconductor wafer and chip production is set to hit an all-time high this year and exceed $50 billion in 2018, as nearly 300 fabrication facilities are upgraded.
The figures, from the US-headquartered Semiconductor Equipment and Materials International (SEMI) industry association, come as chip makers gear up for their next production “nodes” and pave the way towards the era of extreme ultraviolet (EUV) lithography.
Semiconductor production equipment represents one of the largest global markets for lasers, and with the all-important EUV sources inside next-generation lithography scanners from ASML built around laser-driven plasmas, the size of that market should be set to grow as EUV gains traction.
SEMI reports that total equipment spending rose 13 per cent in 2016, to $41 billion. And it is predicting that a 24 per cent jump in bookings over the same period will translate to an all-time annual record spend of $46 billion this year and close to $50 billion in 2018.
If correct, that would represent the first time that spending has risen in three consecutive years since the 1990s.
At a cost of more than $100 million per scanner, and after a tortuous three decades in development, the latest EUV lithography tools from ASML will become responsible for a growing chunk of that total.
During last month’s SPIE Advanced Lithography conference in San Jose, ASML detailed the latest progress with its “NXE:3400B” tools – the equipment now earmarked for volume production, expected to begin in late 2018 or early 2019.
Marc van de Kerkhof, ASML’s product systems engineer for the 3400B tool, outlined improvements from the “NXE:3350” generation that are geared towards hitting the elusive wafer throughput target of 125 wafers per hour regarded as a benchmark for volume production.
Central to that progress is raising source power and availability, and ASML demonstrated a new record throughput of 104 wafers per hour as recently as January – the first time it has reached a triple-digit number, something described by van de Kerkhof as a “big milestone”.
That was achieved with an EUV source power of 148 W, and with a new best of 210 W demonstrated on a tool at its own development site – up from 125 W a year ago - the 125 wafers per hour target set by the company for 2017 looks well within reach.
Also speaking in San Jose, Intel senior principal engineer Britt Turkot said that with 14 of ASML’s EUV tools now being put through their paces in the field, the wealth of data now being produced by the equipment promised that the end of the “long and winding road” was at last in sight.
She expects the 210 W source power demonstrated internally to be replicated in the field quickly, and reported progress in other source components that have proved problematic - such as the tin droplet generator and collector optics.
Turkot also pointed to Gigaphoton’s "promising" EUV source development, which uses a different drive laser to ASML’s Trumpf-powered design, with lower levels of tin debris and a higher conversion efficiency standing out.
With the requisite power now apparently in place, the key for Intel is more predictable tool performance and improved system availability.
And with six out of eight key “readiness” metrics now ticked off, it is the development of defect-mitigating pellicles suitable for volume manufacturing, and actinic mask inspection tools that remain on EUV's "to do" list.
ASML appears to have risen the first of those challenges, with its internal development of a “spectral purity membrane” now proceeding to full commercialization.
Turkot described that as a remarkable improvement on the pellicle situation compared with a year ago, although she did stress that there was no room for slippage in the anticipated delivery of a fully commercial version later this year for EUV to meet its latest implementation schedule.
And while actinic mask development does not represent a “show-stopper” of a problem, wafer yields would be impacted without it, with implications for cost and throughput that could affect the timing of EUV’s introduction.
All in all, the remaining uncertainties mean that it is still not exactly clear when Intel will introduce EUV in its processes. “EUV lithography is highly desirable for the 7 nm node but will only be used when it is ready,” Turkot said, stressing that sustained, predictable tool availability was more important that maximizing wafer throughput figures.
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