20 Jun 2013
Chip targets high-speed, high-resolution imaging applications - such as next-gen HDTVimec, Leuven, Belgium, has demonstrated a new CMOS image sensor that is capable of capturing 12-bit 4,000 x 2,000pixel progressive images at 60 frames per second.
Based on a “stagger-laced dual exposure” design, the image sensor, which was co-developed with Panasonic, was processed using imec’s 130nm CMOS process on 200mm silicon wafers to achieve the high-speed and high-quality imaging, at reduced output bit rate.
The number of pixels on image sensors deployed in video and still cameras continues to increase, along with the frame rate and bit resolution requirements of the images. “4K2K” is widely expected be the next-generation broadcasting format, offering an increase by a factor of two in both horizontal and vertical resolution compared to current state-of-the-art High Definition TV.
The new image sensor chip is a floating diffusion shared 4T pixel imager, with a pitch of 2.5µm and a conversion gain of 70μV/e-, which allows for both a classical rolling shutter or stagger-laced scanning mode.
The 4K2K 60fps imaging performance is realized by 12-bit column-based delta-sigma A/D converters. The stagger-laced scanning method improves imaging sensitivity and realizes a 50% reduction in output data rate by alternating the readout of two sets of horizontal pixel pairs arranged in two complementary checkerboard patterns. Additionally, the overall power consumption of the imager is less than 2W.
Rudi Cartuyvels, Senior Vice President Smart Systems & Energy Technologies at imec, commented, “This is an important milestone for imec to demonstrate our capability to co-design, prototype and manufacture high performance CMOS image sensors in our 200 mm CMOS fab,” commented.
About the Author
Matthew Peach is a contributing editor to optics.org.
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